[Letux-kernel] replacement for omap_hsmmc: hackish try to enable sdio interrupts

H. Nikolaus Schaller hns at goldelico.com
Fri Aug 31 19:51:48 CEST 2018

> Am 31.08.2018 um 19:18 schrieb Andreas Kemnade <andreas at kemnade.info>:
> Hi,
> On Fri, 31 Aug 2018 17:52:52 +0200
> "H. Nikolaus Schaller" <hns at goldelico.com> wrote:
>> Hi,
>>> Am 31.08.2018 um 17:08 schrieb Andreas Kemnade <andreas at kemnade.info>:
>>> Hi,
>>> I have finally created a better patch for above-mentioned commit, so it can be
>>> upstreamed. It works with good performance. After testing on a letux 3704 (so I have both with and without
>>> level shifter), I will probably send the patch upstream. It seems te be independant
>>> of the other dt things.  
>> Looks good. If we have something ready for upstreaming, please do so!
>> Just spotted a typo in the commit message:
>> s/preperly/properly/
>> What I am not sure is about the code style to have blank lines between pinmux entries or have not...
>> But DTS maintainers will complain and the compiler will make the same DTB out of it.
> well, if it is only that... I could live with both. No blank lines does
> not look well, you do not see where the comment belongs. Single line
> seems to be accepted, at least in former times, but checkpatch does not
> like it.
>>> Just one question: is the sdmmc2_dat4.sdmmc2_dir_dat1 setting correct?
>>> It differs from u-boot.   
>> Hm. Good question. I would guess that kernel DT is correct and u-boot is untested, i.e. may be wrong. AFAIK, no GTA04 uses sdmmc2 in u-boot...
> kernel had no mmc2 pinmux (or have I overlooked something?), so it was
> relying on uboot to do the job, well lets see how well the pinmux works
> with level-shifter in action.

Ah, ok!

Hm. Well...

Then we should carefully study schematics + required pinmux settings.

So this means
* AF4, AG4, AH4, AH5 are mmc2 bidirectional
* AG5 is cmda
* AE2 is clka
* AE3 is clkf
* AF3 is cmddir
* AH3 is dat123dir
* AE4 is dat0dir

now we have to look up the pinmux mode for these pads in the dm3730 data sheet...
* AF4	mmc2_dat3 = mode 0	gpio 135	I/O
* AG4	mmc2_dat2 = mode 0	gpio 134	I/O
* AH4	mmc2_dat1 = mode 0	gpio 133	I/O
* AH5	mmc2_dat0 = mode 0	gpio 132	I/O
* AG5	mmc2_cmd = mode 0	gpio 131	O
* AE2	mmc2_clk = mode 0	gpio 130	I/O
* AE3	mmc2_clkin = mode 1	gpio 139	I
* AF3	mmc2_dir_cmd = mode 1	gpio 138	O
* AH3	mmc2_dir_dat1 = mode 1	gpio 137	O
* AE4	mmc2_dir_dat0 = mode 1	gpio 136	O

in other words: all mmc2 pads are mode 0 and the 4 pads (re)used from mmc3 are to be mode 1.

and finally find out the pin mux register addresses in the TRM (but I assume that this is already ok).

So you can compare my theory with the code you find and plan to use...

BTW: the GTA04A5 has no level shifter. I haven't looked up if it sets a different mode?
It will ignore the O pins but what about mmc2_clkin? Ok, AE3 is already re-muxed to be WLAN-IRQ.


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