[Letux-kernel] x1600: how RAM size is determined

H. Nikolaus Schaller hns at goldelico.com
Sat Mar 2 19:13:46 CET 2024


Hi Paul,

> Am 02.03.2024 um 19:01 schrieb Paul Boddie <paul at boddie.org.uk>:
> 
> On Saturday, 2 March 2024 18:35:17 CET H. Nikolaus Schaller wrote:
>> 
>> The chip type is logged to the console by SPL.
>> 
>> For the x1600 (not x1600e) case this contains a record with .h.id =
>> 0x0000001b for some 32 MB RAM.
> 
> Without looking into any code, I notice that the DDR configure register (DCFG) 
> has fields for the row and column address widths:
> 
> <29:27> ROW1
> <26:24> COL1
> 
> <13:11> ROW0
> <10:8>  COL0
> 
> I can imagine that something might need to be written to these fields. If it 
> is that value of 0x1b,


No, this 0x1b is an index into a table that is generated during UBoot-Compile.
The table has a lot of timing configs for all these registers and it may just be 
a coincidence if you see 0x1b in both.

> then it might correspond to 0b011011, or ROW=0b11 and 
> COL=0b11, which could then mean a 15-bit row address and an 11-bit column 
> address. But that would yield a 26-bit combined address (or 64MB).
> 
> Meanwhile, for reference, the processor identifier for the X1600 is described 
> as follows:
> 
> "2.2 PRID of X1600-CPU
> Processor ID register (CP0 Register 15, select 0) in XBurst CPUs is a read-
> only register being used to identify implementation detail of each SOC's CPU. 
> Please refer to the programming manual of XBurst CPU for detail of the 
> register. For X1600, its value is 0x00D0000"

I think this is used somewhere in the MIPS startup code and was initially
missing. Ah, yes:

https://git.goldelico.com/?p=letux-kernel.git;a=blobdiff;f=arch/mips/include/asm/cpu.h;h=557305261b4f0b28f11f8ae8c2a90aafdc4cd2dd;hp=ecb9854cb4324820aede937e29ad9e40db3fb0e6;hb=bc22fd994f52e6b1c0a64b35454b0da6abe606f2;hpb=d206a76d7d2726f3b096037f2079ce0bd3ba329b

There we already have this constant. We just have to differentiate between
the revisions.

But it does not differentiate between the different RAM variants.

> I'm not sure if I really have any answers here!

No problem, we are all learners...

I, for example, just learned that we do NOT need to add x1600e to the compatible
list here:

https://git.goldelico.com/?p=letux-kernel.git;a=blobdiff;f=arch/mips/generic/board-ingenic.c;h=cc2e31ad96491c3f90553c4bdf1a9d59889f72a7;hp=1f4906875e7bc2ce5644438f7bd417261f4f1ed9;hb=bc22fd994f52e6b1c0a64b35454b0da6abe606f2;hpb=d206a76d7d2726f3b096037f2079ce0bd3ba329b

Since RAM size and initialization things should have been done by SPL (like
on all processors I know of).

BR,
Nikolaus



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