H. Nikolaus Schaller
hns at goldelico.com
Sun Feb 21 18:45:32 CET 2021
> Am 21.02.2021 um 17:42 schrieb H. Nikolaus Schaller <hns at goldelico.com>:
> The most mysterious part for me is still how the controller switches from
> write to read mode.
> At the moment it looks as if it is very simple: if 9 bits have been sent
> and there was no new DRF=1 it sets TEND=1 and goes to read mode. Read mode
> sets DRF=1 automatically every 9 bits. Each such event generates an IRQ.
Just for the notes:
The flow charts seem to confirm this idea.
For Write Operation there is a wait for TEND=1 after sending the last byte
and setting STO to 1 to complete the operation. According to my theory
this is the moment where the last byte has been written and the ACKF bit
For Read Operation a similar thing happens after writing the address which
is the last (and only) byte that is sent.
They have just swapped the check for TEND=1? and ACKF=0?.
Then they start reading.
And before the last byte read they set the AC to 1 so that the bus master
confirms to the slave.
This indicates that the sending shift register is still running - just
not sending bits (or by sending dummy data words 0xff which may be
done by setting DRF = 0).
Very likely missing is to send a STO as well.
This would indeed mean that switching to read mode is done by letting
the shift counter / shift register drain.
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