[Letux-kernel] Memory freeze and timing CI20

Zhou Yanjie zhouyanjie at wanyeetech.com
Mon Feb 15 21:05:11 CET 2021


On 2021/2/16 上午3:56, Zhou Yanjie wrote:
> Hi Nikolaus,
>
> On 2021/2/15 下午7:12, H. Nikolaus Schaller wrote:
>> Hi,
>> sorry for the delay on my side now...
>>
>>> Am 11.02.2021 um 16:15 schrieb Zhou Yanjie <zhouyanjie at wanyeetech.com>:
>>>
>>> Hi Nikolaus,
>>>
>>>
>>> Sorry, I got caught up in other thins last few weeks.
>>>
>>>
>>> On 2021/2/5 下午2:53, H. Nikolaus Schaller wrote:
>>>> Hi,
>>>> I got a hint from a member of the Pyra community who had been 
>>>> following
>>>> the OMAP5 + DDR3 timing issues, that the jz4780/CI20 may have 
>>>> similar issues.
>>>
>>> Could you describe the specific phenomenon?
>> I do not know more than described in the pull request description
>>
>>>> https://github.com/MIPS/CI20_u-boot/pull/18
>> The author says
>>
>> "This fixes a few timing errors in the memory initialization routine, 
>> specifically the minimum self-refresh time which was too low for both 
>> Samsung and Hynix chip, as well as the four bank activation time and 
>> the exit-power-down-to-active-command delay for the Samsung ones. The 
>> changes are based on the memory chips' most recent datasheets as well 
>> as the JZ4780 manual and have fixed all memory-related freezes I've 
>> been experiencing with my board."
>>
>> But I haven't observed memory related issues myself. BTW it is not 
>> clear how to
>> easily distinguish that from other freezes.
>>
>> What we had was a memory timing issue on the omap5. There stability 
>> did clearly depend
>> on the installed memory chips (there were two variants) and tweaking 
>> the memory timings
>> did fix it for all. It had something to do with automatic timing 
>> measurements and corrections
>> of the DDR3 chips. This was not enabled correctly on omap5.
>
>
> I'm glad to hear you fixed the timing issue, but unfortunately I am 
> not familiar with the memory timing training. The parameters in u-boot 
> I transplanted are all provided by Ingenic directly. I may not be able 
> to help much in this part.
>
>
>>>   And witch version u-boot do you use?
>> I use this u-boot:
>>
>> https://git.goldelico.com/?p=letux-uboot.git;a=shortlog;h=refs/heads/ci20-v2013.10 
>>
>>
>> seems to be a 2013.10 u-boot with a lot of fixes up to 2017.
>
>
> I am also using this version, and have not encountered timing issues 
> for the time being.
>
>
>>> It seems that now the u-boot mainline (after version 2019.01) also 
>>> supports CI20.
>> So it could be that the mainline u-boot already includes the patch
>>
>> https://github.com/MIPS/CI20_u-boot/pull/18/commits/3c4bdbd749edc344abf11823282363d79c1d5eeb 
>>
>
>
> I'm not too sure. To be honest, I haven't read the mainline u-boot 
> code of CI20 carefully. I am trying to port the u-boot of X1000 and 
> X1830 from the 2013.07 version (provided by Ingenic) to the 2015.04 
> version to provide support for FIT.
>
>
>>>
>>>> I am not sure if it is needed or not since my board works well 
>>>> without - except
>>>> the freezes I had observed with SMP but I did not relate this to 
>>>> memory timing.
>>>>
>>>> There is a patch floating around:
>>>>
>>>> https://github.com/MIPS/CI20_u-boot/pull/18
>>>>
>>>> I have checked an in my U-Boot it is not included but could be added.
>>>>
>>>> What do you think?
>>>>
>>>> BTW: what is the status of the SMP / Cache driver?
>>>
>>> It seems to work normally based on 5.10.7, I will send it to you later.
>> Fine and thanks!
>
>
> The new patch is in the attachment, you only need to replace thee 
> original [10/13] patch with it. So far, there is no abnormality in the 
> test of X1000 and X1830, and there is also no abnormality in the 
> single-core test of JZ4780, the dual-core test has not yet been 
> completed.
>

Sorry, the attachment of the last email was sent wrong, the attachment 
of this email is correct.


>
> Thanks and best regards!
>
>
>>
>>> Happy Chinese New Year!
>> BR and same to you,
>> Nikolaus
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