[Letux-kernel] Letux/Alpha 400: small progress with sound

[H. Nikolaus Schaller]

> Am 28.04.2021 um 21:58 schrieb H. Nikolaus Schaller <hns at goldelico.com>:
> 
> Hi Paul,
> 
>> Am 28.04.2021 um 21:39 schrieb Paul Boddie <paul at boddie.org.uk>:
>> 
>> On Wednesday, 28 April 2021 20:19:15 CEST H. Nikolaus Schaller wrote:
>>> 
>>> I have hacked some ioremap() into jz4740_i2s_trigger() to be able to modify
>>> pinctrl on the fly and read the gpio bits directly.
>>> 
>>> There is clock activity on both BITCLK and SYNC obviously coming from the
>>> codec. And switching to ping function 0x2 makes these pins an output.
>>> 
>>> So I think we can rule out codec and pinctrl problems as the main blocking
>>> point for completely stuck communication. It still may happen that there is
>>> no sound if we fix that but aplay Front_Center.wav should finish playing
>>> after ca. 3 seconds.
>>> 
>>> There remains only the AC97/I2S driver as the location of the issue.
>> 
>> I would have to look at it properly to have an opinion about it. Is there some 
>> DMA involvement in this as well?
> 
> Yes... But it looks as if the I2S interface isn't properly initialized and therefore
> gets stuck. No interrupt, no timeout no anything. Just waiting after setting up
> everything. A register dump seems to indicate that the TX FIFO is being filled.
> So maybe even DMA might work in this case but I can't know...
> 
> What I found is that there is very special code in the old driver:
> 
> 	https://git.goldelico.com/?p=letux-kernel.git;a=blob;f=sound/soc/jz4740/jz4740-i2s.c;h=c58d9c3c844d242da1a8d357270eec87197b385c;hb=86df48ade42a3e852b10b26f11676da0e8c13ccc#l200
> 
> It does some initialization, then a mdelay, a reset and the same again...
> 
> But I can't find anything similar here:
> 
> 	https://elixir.bootlin.com/linux/latest/source/sound/soc/jz4740/jz4740-i2s.c#L416
> 
> Here, it simply sets the reset bit and writes the new config. Assuming that the
> controller reset can be done in one processor write cycle.
> 
> Maybe the jz4730 hardware needs more time to reset and hence setting the config
> is lost.

Ok, the jz4780 has (at least 99%) the same i2s as the jz4740 which has 95% the same
as jz4730. This is good since it means I can compare the same driver code on both...

What I have found in the programming manuals of all jz47* is:

	Please set this bit to 1 to stop BIT_CLK when change AICFR.AUSEL and AICFR.BCKD.

But I can't find that in the (new) driver. This might explain why the driver or
devmem2 does not set AUSEL.

So my plan was to compare to CI20.

But it turns out that the CI20 has no sound. We can try to port it from FreeBSD:

	https://github.com/freebsd/freebsd-src/blob/master/sys/gnu/dts/mips/ingenic/jz4780.dtsi

But it uses the internal codec: 

		codec: codec at 100200a4 {
			compatible = "ingenic,jz4780-codec";
			reg = <0x100200a4 0x8>;

			clocks = <&cgu JZ4780_CLK_I2SPLL>;
			clock-names = "i2s";

		};

for which we have no Linux driver :(

BTW: there seem to be two i2s instances on jz4780 (at least from DMA and IRQ) but
there is only one base address.

Cul-de-sac...

BR,
Nikolaus