[Letux-kernel] [PATCH 08/20] fixup! Add clock driver for the JZ4730

[Lubomir Rintel]

I took a wild guess at parents since there doesn't seem to be a data
sheet. I'm not using the SPI at all, but I need to fill in the spot in
the clock array because the CGU driver is not happy at all when it's
sparse:

  [    0.000000] ingenic_register_clock: no clock type specified for '(null)'

Signed-off-by: Lubomir Rintel <lkundrak at v3.sk>
---
 drivers/clk/ingenic/jz4730-cgu.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/clk/ingenic/jz4730-cgu.c b/drivers/clk/ingenic/jz4730-cgu.c
index 3a775906f7724..34a6dedabb6c2 100644
--- a/drivers/clk/ingenic/jz4730-cgu.c
+++ b/drivers/clk/ingenic/jz4730-cgu.c
@@ -182,6 +182,13 @@ static const struct ingenic_cgu_clk_info jz4730_cgu_clocks[] = {
 		.mux = { CGU_REG_CFCR, 29, 1 },
 	},
 
+	[JZ4730_CLK_SPI] = {
+		"spi", CGU_CLK_MUX | CGU_CLK_GATE,
+		.parents = { JZ4730_CLK_PLL, JZ4730_CLK_PLL_HALF, -1, -1 },
+		.mux = { CGU_REG_CFCR, 31, 1 },
+		.gate = { CGU_REG_MSCR, 12 },
+	},
+
 	[JZ4730_CLK_MMC] = {
 		"mmc", CGU_CLK_GATE,
 		.parents = { JZ4730_CLK_MSC16M, JZ4730_CLK_MSC24M, -1, -1 },
-- 
2.28.0