[Letux-kernel] [PATCH 05/20] fixup! Add clock driver for the JZ4730.

[Lubomir Rintel]

Fix the clock type for the PCLK divisor.

Signed-off-by: Lubomir Rintel <lkundrak at v3.sk>
---
 drivers/clk/ingenic/jz4730-cgu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/ingenic/jz4730-cgu.c b/drivers/clk/ingenic/jz4730-cgu.c
index 547ce66b6ae43..d1c1e98f34963 100644
--- a/drivers/clk/ingenic/jz4730-cgu.c
+++ b/drivers/clk/ingenic/jz4730-cgu.c
@@ -125,7 +125,7 @@ static const struct ingenic_cgu_clk_info jz4730_cgu_clocks[] = {
 	},
 
 	[JZ4730_CLK_PCLK_PLL] = {
-		"pclkdiv", CGU_CLK_MUX,
+		"pclkdiv", CGU_CLK_DIV,
 		.parents = { JZ4730_CLK_PLL, -1, -1, -1 },
 		.div = {
 			CGU_REG_CFCR, 8, 1, 4, 20, -1, -1,
-- 
2.28.0