[Letux-kernel] [PATCH 04/20] fixup! Add clock driver for the JZ4730.

[Lubomir Rintel]

The parent mux is already called "mclk" -- use a different name for the
divisor.

  [    0.000000] ingenic_register_clock: failed to register clock 'mclk'
  [    0.000000] jz4730_cgu_init: failed to register CGU Clocks: -17

Signed-off-by: Lubomir Rintel <lkundrak at v3.sk>
---
 drivers/clk/ingenic/jz4730-cgu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/ingenic/jz4730-cgu.c b/drivers/clk/ingenic/jz4730-cgu.c
index 14f542b7f5793..547ce66b6ae43 100644
--- a/drivers/clk/ingenic/jz4730-cgu.c
+++ b/drivers/clk/ingenic/jz4730-cgu.c
@@ -140,7 +140,7 @@ static const struct ingenic_cgu_clk_info jz4730_cgu_clocks[] = {
 	},
 
 	[JZ4730_CLK_MCLK_PLL] = {
-		"mclk", CGU_CLK_DIV,
+		"mclkdiv", CGU_CLK_DIV,
 		.parents = { JZ4730_CLK_PLL, -1, -1, -1 },
 		.div = {
 			CGU_REG_CFCR, 16, 1, 4, 20, -1, -1,
-- 
2.28.0