[Letux-kernel] jz4780 read out LCDC setup for HDMI
H. Nikolaus Schaller
hns at goldelico.com
Thu Jun 4 20:58:34 CEST 2020
> Am 04.06.2020 um 19:29 schrieb Paul Boddie <paul at boddie.org.uk>:
> On Thursday 4. June 2020 17.18.09 H. Nikolaus Schaller wrote:
>> I have booted the latest letux-5.7 and now, the lcdc got initialized!
>> So maybe something has improved in the DRM subsystem without our activity.
>> root at letux:~# cat /sys/kernel/debug/regmap/13050000.lcdc0/registers
>> 00: 00f00840
> This is the configuration register, set up fairly normally.
>> 04: 00000003
>> 08: 0000000d
> These are the sync pulse definitions.
>> 0c: 0520026e
> These are the "virtual" display dimensions: 1312x622.
>> 10: 011b051b
>> 14: 0014026c
> And these are the horizontal and vertical picture settings: 283-1307 and
> 20-620, suggesting a resolution of 1044x600, I guess.
>> 18: 00000000
>> 1c: 00000000
>> 20: 00000000
>> 24: 00000000
>> 28: 00000000
>> 2c: 00000000
> These should probably all be zero.
>> 30: 24002008
> This indicates that the LCD controller is enabled. It's the fairly standard
> configuration for the controller with end-of-frame interrupts enabled, and so
>> 34: 00000004
> Here, we see the "FIFO 0" underrun condition, although that occurs in the
> 3.0.8 kernel, too, from your earlier output. Maybe I shouldn't be so worried
> about that.
>> 38: 00000000
> This should be the frame identifier (see below).
>> 3c: 00000000
> This should probably be zero.
>> 40: 0e2ee000
> This is the DMA descriptor #0 physical address.
>> 44: 01000000
>> 48: deafbead
>> 4c: 00096000
> And these are the framebuffer physical address, frame identifier and command
> (framebuffer size of 614400 words).
>> 50: 0007626f
> This is the DMA descriptor #1 physical address.
>> 54: 01050010
>> 58: 2d544d47
>> 5c: 00000032
> These are the registers affected by descriptor #1, quite possibly not set up
> to sensible values.
>> root at letux:~#
>> Still there is no image.
>>> I did now boot with the Imagination system in Flash memory.
>>> It is an 3.0.8-Kernel. And my HDMI monitor works out of the box.
>> I did boot with both kernel and did run my scripts (using devmem2)
>> on both devices. The register values of each kernel are attached.
> Thanks for doing this: it may be useful to see what differences there are.
> Looking at the 3.0.8 LCD controller registers, there are many familiar things
> from the source code (and from the 3.18 sources).
Indeed. The more working / non-working examples we have the better we
can understand what makes the difference.
>> Main difference for the PHY seems to be in the audio area, but there
>> are also some HDMI_IH, HDMI_VP and HDMI_FC registers where I don't
>> have any idea what they are about.
> IH is interrupt handling, VP is video packetization and FC is frame composer.
> Although the latter two are not entirely self-explanatory, I now have some
> idea of what they do.
Ok, good to know.
>> As mentioned above the LCDC has been initialized (without me
>> recognising this first). But register values are completely different.
> One thing to note about the 3.0.8 kernel is that it might not be very clever
> about picking a display resolution. At the moment, though, the upstream LCD
> driver is not likely to be doing anything specific for the JZ4780, and I think
> that some of the extra features may be needed to produce a picture via HDMI,
> such as the RGB control register. It is also possible that the on-screen
> display (OSD) functionality is somehow involved.
I checked again and ingenic_drm_crtc_update_timings() is still never called.
It takes ca. 40 seconds for ingenic_drm_probe() to complete. Probably by
some timeout ([CRTC:32:crtc-0] vblank wait timed out).
Therefore I think the key problem is that ingenic_drm_crtc_update_timings()
is not called when it should leaving the LCDC in a partially initialized
Well, ingenic_drm_crtc_atomic_flush() should call it if "drm_atomic_crtc_needs_modeset".
It should also set some pixel formats and set the clock rate. If that does
not happen we have to expect a problem...
I tried to make it always happen and then ingenic_drm_crtc_update_timings()
is called. But still only timeouts.
Well the timeouts may be related to that ingenic_drm_irq_handler() is never called.
And I could not see a call to ingenic_drm_enable_vblank(). This means
[ 42.809191] WARNING: CPU: 0 PID: 5 at drivers/gpu/drm/drm_atomic_helper.c:1495 drm_atomic_helper_wait_for_vblanks+0x220/0x2a8 [drm_kms_helper]
[ 42.809198] [CRTC:32:crtc-0] vblank wait timed out
waits without enabling vblank before... This seems to be called by
Finally, ingenic_drm_encoder_atomic_mode_set() isn't called either.
So basically the ingenic-drm driver is probed but not initialized completely.
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