[Gta04-owner] CPU, Memory

Glenn Moeller-Holst glenn.mh.dk at gmail.com
Tue Mar 8 20:32:15 CET 2011


At 8:45 +0100 07/03/11, Dr. H. Nikolaus Schaller wrote:
>Hi Glenn,
...
>  > How is that possible ;-) - you have an 8-layer PCB and PoP 
>memory? (ironically)
>
>Well, PoP allows us to reduce from 16 to 8 layers :)
...
>  > * keep high current wires short
>
>and wide.
>
>This is part of the problem. Since wide enough power traces leave
>almost no space for other signals. So we have to find the best
>compromise between wide power traces and fan-out of the other
>signals.
>
>The key problem is connecting the 284 balls TPS65950 with the 512 balls
>OMAP3. Both have a pitch of 0.4mm and the width of the wires don't allow
>to add traces that can pass between two pads. I.e. any inner row must
>go within the pad (Via-In-Pad technology) to one of the inner layers.
...
>We have relaxed a little and got new energy to solve the remaining
>issues (other teams and companies have shown that it can be solved,
>so there is no technical reason that we can't).
>
>BR,
>Nikolaus
>
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>Gta04-owner at goldelico.com
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Hi Nikolaus

TPS65950 - oh my - what a chip - to many connections...

Why not let the CPU and memory ride on top of TPS65950?

I looked at pdf-page 12, 13, 33 and 66 - they have "thrown" a lot of 
functionalty into that chip:

TPS65950 Data Manual (Rev. E):
http://www.ti.com/lit/gpn/tps65950

-

You have of cause looked at page 12...14 and 23 - and especially 
8...9 (wire between vias)? - could you ask them of a 
reference/example PCB design? They ought to be eager to help 
costumers?:

TPS65950 Layout Guide (Rev. A):
http://www.ti.com/litv/pdf/swcu055a

BR,

Glenn


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