[Letux-kernel] X1600 / LX16 support - here: adding MMC

H. Nikolaus Schaller hns at goldelico.com
Fri Feb 9 18:35:38 CET 2024



> Am 09.02.2024 um 18:20 schrieb H. Nikolaus Schaller <hns at goldelico.com>:
> 
>>> So it will indeed be interesting to see how the MSC registers are
>>> initialized. And clock dividers and registers. And pinctrl. Will just need
>>> a little time for hacking this into the kernel code.
> 

Test result of hacking jz4740_mmc_set_clock_rate()

[    0.000200] mmc0: clock 0Hz busmode 2 powermode 1 cs 0 Vdd 21 width 1 timing 0
[    0.000200] jz4740_mmc_set_ios
[    0.000200] jz4740_mmc_set_ios: MMC_POWER_UP
[    0.000200] input: gpio_keys as /devices/platform/gpio_keys/input/input0
[    0.000200] clk: Not disabling unused clocks
[    0.000200] mmc0: clock 400000Hz busmode 2 powermode 2 cs 0 Vdd 21 width 1 timing 0
[    0.000200] jz4740_mmc_set_ios
[    0.000200] jz4740_mmc_set_clock_rate
[    0.000200] jz4740_mmc_set_clock_rate: clk_set_rate(50000000)
[    0.000200] jz4740_mmc_set_clock_rate: real_rate=35000000
[    0.000200] jz4740_mmc_set_clock_rate: writew(00000007, JZ_REG_MMC_CLKRT)
[    0.000200] jz4740_mmc_set_ios: MMC_POWER_ON
[    0.000200] jz4740-mmc 13450000.mmc: Ingenic SD/MMC card driver registered
[    0.000200] jz4740-mmc 13450000.mmc: Using DMA, 4-bit mode

We strangely see that clock 400000Hz is translated into 50 MHz which is limited
by the clock to a lower rate.

Well, there is real magic going on. The clock rate of 400 kHz is just used to
calculate a new divisor. The clock itself is running at its max rate.

Which means we tell the MSC to divide the 35 MHz clock by 7. Because it is limited
to 7.This wold mean 5 MHz. But where do the 3.5 MHz come from I have seen?
Or is div some 2^ divider factor?

Yes, CLKRT:

000: DEV_CLK
001: 1/2 of DEV_CLK
010: 1/4 of DEV_CLK
011: 1/8 of DEV_CLK
100: 1/16 of DEV_CLK
101: 1/32 of DEV_CLK
110: 1/64 of DEV_CLK
111: 1/128 of DEV_CLK
This field must be set to 0 when the controller works during normal
writing or reading.

So the 7 means 1/128 which would be ~273 kHz.

1. can we find out what U-Boot assumes for this divisor?
(probably yes: read 0x13460008 = JZ_REG_MMC_CLKRT)

2. this strengthens the theory that the MSC is in low power mode
Which register can we read to get the status?
jz4740_mmc_set_clock_rate() is a good location for printing
all registers w/o ioremap (the MSC base address is known!)

BR,
Nikolaus


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