[Letux-kernel] jz4730 Ethernet
H. Nikolaus Schaller
hns at goldelico.com
Fri Mar 12 13:04:45 CET 2021
Hi Paul,
> Am 11.03.2021 um 22:48 schrieb Paul Boddie <paul at boddie.org.uk>:
>
> On Thursday, 11 March 2021 13:38:05 CET H. Nikolaus Schaller wrote:
>>
>> just a small note: mii does NOT depend on generic DMA working (only MMC does
>> so far):
>>
>> The Ethernet MAC controller uses a dedicated DMA controller to transfer data
>> between the Ethernet MAC module and the host memory.
>>
>> It is very similar to the DMA descriptors of the LCDC.
>> And the jz4730 ethernet driver has code to do the setup of the buffers.
>
> This is very promising and perhaps time-saving, too. I should really look at
> the manual and see what the details are.
more good news:
* my reworked driver seems to send out valid ethernet packets
* because my router did recognize a new device on the LAN and did report the MAC address I had passed when loading the module
* after manually resetting the ETH irq bit in ICMR I also did see ethernet receive interrupts
* it seems as if the received packets do not reach DHCP because that fails to work
This all means the PHY does not need to be in DT and does not need a dedicated driver :)
We may even omit the 'mdio' node in DT because it is not used anywhere as far as I can see.
Here is what the ifconfig statistic says after some experimentations (and setting a manual IPv4 address):
eth0 Link encap:Ethernet HWaddr 00:0a:0b:0c:0d:ff
inet addr:192.168.2.130 Bcast:192.168.2.255 Mask:255.255.255.0
inet6 addr: fe80::20a:bff:fe0c:dff/64 Scope:Link
inet6 addr: 2001:16b8:26a4:e200:20a:bff:fe0c:dff/64 Scope:Global
UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
RX packets:211 errors:0 dropped:80 overruns:0 frame:0
TX packets:0 errors:1 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:1000
RX bytes:20847 (20.3 KiB) TX bytes:1417 (1.3 KiB)
So (again) we have a problem that the IRQ mask is not set up properly or automatically.
We may have another bug in irq-ingenic.c
The gaps-to-success are now:
* make the driver transmit & receive properly
* unmask the interrupt in time
BR,
Nikolaus
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