[Letux-kernel] jz4730-i2c - clocksource

Paul Boddie paul at boddie.org.uk
Wed Mar 3 23:35:26 CET 2021


Sorry not to have responded recently! I have been reading the messages, but I 
don't have many ideas at the moment.

> I have added another piece of trace code.
> There was another bug that ingenic_tcu_clocksource_init()
> did disable the timer underrun interrupt. And it was nowhere
> enabled in the driver.
> See
> 	https://git.goldelico.com/?p=letux-kernel.git;a=blob;f=drivers/clocksource/
> ingenic-timer.c;h=c6c17c856a15078f9da8e10fe57ca6a5adc0c68a;hb=refs/heads/let
> ux/jz4730-v5#l263
> The mask also resets TCU_JZ4730_TCSR_EN to 0 disabling underflow interrupts.

Here, it is possible that the mismatch between JZ4730 and JZ4740 confuses 
things. TCSR on the JZ4730 includes interrupt control bits, whereas TCSR on 
the JZ4740 only concerns itself with configuring and enabling the timer.

So, the timer initialisation code is aiming to reset the timer to a base 
state, but on the JZ4740 it will not change the interrupt configuration. 
However, the code for the JZ4730 (as I wrote it, I guess) will also disable 
the interrupts.

> Now with my logging code I can see that the timer is decrementing
> and when underrunning, OST0 is flagged in ICSR and IPSR.
> But this does not trigger any interrupt handler, the bit remains set
> and nothing happens.

Looking at the Fiasco support for the Minibook, useful as a checklist, I do 
the following to get the OST/TCU working:

* Clear the IRQ underflow flag in TCSR
* Set the IRQ enable flag in TCSR
* Set the enable flag in TER

The equivalent for the JZ4740-based Ben NanoNote involves this:

* Clear the "full" IRQ flag using TFCR (the clearing variant of TFR)
* Clear the "full" IRQ mask flag using TMCR (the clearing variant of TMR)
* Set the enable flag using TESR (the setting variant of TER)

Oddly, I don't see any use of the mask registers in the Linux drivers, but the 
masks will be clear by default and thus cause interrupts to be delivered, 
anyway. Meanwhile, the JZ4730 will not have the interrupts enabled in TCSR by 

I don't really find much of this easy to follow, but it is very possible that 
we (mostly I) missed something earlier and we (mostly you) are having to track 
down what that was. Obviously, I am rather sorry about that!

Thanks for keeping going, though!


P.S. I just fetched your updated code, so I will try and find some time to 
take a look in the near future.

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