[Letux-kernel] JZ4730 LCD controller (was Re: [PATCH 00/20] A bunch of JZ4730 fixups for letux-kernel)
paul at boddie.org.uk
Tue Jan 12 22:11:32 CET 2021
On Tuesday, 12 January 2021 20:17:51 CET H. Nikolaus Schaller wrote:
> * suspend/resume with disable/enable lcd
> Note the special code for jz4730!
I think this is mostly configuring pins and the backlight, and it is only
relevant to resuming the operation after sleeping. Hopefully, we will have set
up all the necessary pins and the PWM for the backlight.
> BTW: the driver seems to use a palette to handle different depths - at least
> for small depths. And, there is a daemon that can rotate the framebuffer on
> the fly... Quite elaborated in capabilities but >500% different from the
> modern drm and framebuffer code.
I was going to mention that the legacy driver probably sets up a palette for
low pixel depths because that is how such display modes are intended to be
used. I remember that the original driver for the Ben NanoNote did that, and I
have carried such code forward in the L4Re driver I have made.
> It is also possible to search for CONFIG_SOC_JZ4730 or CONFIG_SOC_JZ4740 to
> see differences. There aren't many. Of course the additional depths and some
> different clock calculations. And minor differences in suspend/resume.
I use the same code in my L4Re driver to support both the Letux 400 and the
Ben NanoNote, so I don't think there will be much to investigate here.
However, the clock configuration aspects might be worth revisiting.
One thing that differs between the legacy code and the manual is the treatment
of the LCD device clock divider: the code maps the value set in the LFR field
of CFCR to a table of divider values, whereas the manual claims that the LFR
field contains the divider value minus one. I noted this in the documentation
page under "Dividers":
The register dump you sent yesterday has the following for CFCR:
0x0d523220 -> 0b1101010100100011001000100000
LFR is bits 15..12 which is 0011 in the above. In the divider table scheme,
this corresponds to a divider of 4, and in the linear scheme it also
corresponds to a divider of 4. I guess it would only make a difference for
higher LFR values.
The dump had the following for CFCR2:
I think this would give a pixel clock divider of 12 (0b is 11, plus one gives
Maybe I could see what register values are set up in my L4Re programs and even
switch the clock configuration to see if it makes a difference.
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