[Letux-kernel] [PATCH 00/20] A bunch of JZ4730 fixups for letux-kernel

H. Nikolaus Schaller hns at goldelico.com
Mon Jan 11 16:27:13 CET 2021

Hi Paul.
I have some progress on the jz4730 display drivers on 5.11-rc3. Well on the LCDC, but not yet
the ingenic-drm driver.

What I have done was to install devmem2 on the old 2.6.24 kernel SD card. Was a little
tricky by having Ethernet but neither telnetd nor sshd running. Well, I could have copied
the files directly to the SD card, but wget did work. Even for https (when ignoring the certificate).

So I was able to read out all cgu/tcu registers and except the lcd and pixel clock dividers
and the second OST on 5.11 all bits are the same. Which makes it more difficult to understand
the overall half-speed effects...

Anyways I played a little with devmem2 on the 5.11 kernel and poked the PWM to work.

And then I could get PWM and the LCDC up and running. The image is like an old analog TV with
weak signals showing quite random moiree :)

This was to be expected because the DMA descriptor isn't pointing to where DRM has alloced
any framebuffer. And it has allocated one. I get an /dev/fb0... But the wrong descriptor
may visualize the stack or some buffers or whatever.

Currently I am trying to figure out why ingenic_drm isn't initializing the LCDC on its own.

A problem seems to be that ingenic_drm_encoder_atomic_check() has no formats.


I think I remember this from the CI20 HDMI work but do not know the solution.

One other thing became clear is that my simple setup does trigger start-of-frame interrupts but
does not handle them. It would only handle EOF interrupts:


So this leads to a high system load. And I have not yet been able to mask this through JZ_REG_LCD_CTRL.

And very generally, the jz4730 is indeed almost identical to the jz4740 lcdc. There just seems
to be some combination with the camera interface. The driver writes (unconditionally) to some 
JZ_REG_LCD_IPUR which does not exist on the jz4730.


This should IMHO be guarded by

	if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU) && priv->ipu_plane)

independently of jz4730 since not all Ingenic SoC have this register and capability.


			devmem2 0x10050000 b 0x8d	# enable PWM
			devmem2 0x10050004 h 0x3f	# period 0x3f
			devmem2 0x10050008 h 0x30	# duty 0x30 of 0x3f
		# attempt to get the LCDC manually up
			# pinmux from 2.6.24-kernel
			devmem2 0x10010040 w 0x55555550	# pinmux PS2, MSC, LCD_D0-D7
			devmem2 0x10010044 w 0x556a5555	# pinmux LCD
			# cgu changes
			devmem2 0x10000000 w 0x0d523220	# CGU_REG_CFCR LFR LCD clock divider
			devmem2 0x10000060 h 0x000b	# CGU_REG_CFCR2 PXFR LPCLK divider
			# lcdc setup
			devmem2 0x13050000 w 0x00000100 #JZ_REG_LCD_CFG
			devmem2 0x13050004 w 0x00000014 #JZ_REG_LCD_VSYNC
			devmem2 0x13050008 w 0x00000050 #JZ_REG_LCD_HSYNC
			devmem2 0x1305000c w 0x037001f4 #JZ_REG_LCD_VAT
			devmem2 0x13050010 w 0x00500370 #JZ_REG_LCD_DAH
			devmem2 0x13050014 w 0x001401f4 #JZ_REG_LCD_DAV
			# stop and mask all interrupts
			devmem2 0x13050034 w 0x00000000 #JZ_REG_LCD_STATE
			devmem2 0x13050030 w 0x24003f8c #JZ_REG_LCD_CTRL
			devmem2 0x13050034 w 0x00000000 #JZ_REG_LCD_STATE
			#devmem2 0x13050030 w 0x2400080c #JZ_REG_LCD_CTRL
			# devmem2 0x13050034 w 0x00000030 #JZ_REG_LCD_STATE
			# these regoszers should have been set up by the lcd driver to point into the framebuffer
			devmem2 0x13050040 w 0x07d52400 #JZ_REG_LCD_DA0
			devmem2 0x13050044 w 0x07500000 #JZ_REG_LCD_SA0
			devmem2 0x13050048 w 0xbeafbeaf #JZ_REG_LCD_FID0
			devmem2 0x1305004c w 0x00002030 #JZ_REG_LCD_CMD0
			#devmem2 0x1305004c w 0xc0002030 #JZ_REG_LCD_CMD0

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