[Letux-kernel] [PATCH 0/3] MIPS: CI20: USB EHCI/OHCI

H. Nikolaus Schaller hns at goldelico.com
Sun Sep 27 17:49:44 CEST 2020


Hi Paul,

> Am 27.09.2020 um 17:11 schrieb Paul Boddie <paul at boddie.org.uk>:
> 
> On Sunday, 27 September 2020 09:06:35 CEST H. Nikolaus Schaller wrote:
>> Hi Paul,
>> 
>> Am 26.09.2020 um 18:53 schrieb Paul Boddie <paul at boddie.org.uk>:
>>> 
>>> Maybe the enable/disable operations need to be defined in the UHC clock
>>> construct instead, though.
>> 
>> Yes, that is what I also would assume. Currently it is just a hack, but the
>> [JZ4780_CLK_UHC] setup breaks if I add custom ops. Maybe it does not manage
>> to handle simple setup for the clock and custom for the OPCR. So we may have
>> to do clock setup in the ops as well.
> 
> Or maybe a "virtual" clock node of some kind is required that only performs 
> the enable and disable operations, just like the JZ4780_CLK_OTGPHY node but 
> consuming the output from JZ4780_CLK_UHC and acting as the actual peripheral 
> clock. Under such circumstances, I don't know what the JZ4780_CLK_OTGPHY would 
> end up doing, apart from simply propagating EXCLK.
> 
> Looking at the manual, I find a few things that might influence all of this:
> 
> USB Parameter Control Register (USBPCR) has a USB_MODE flag that selects USB 
> or OTG operation, plus a SIDDQ flag that is the "OTG PHY analog blocks power 
> down signal".

Yes, that is for OTG.

> 
> USB Parameter Control Register 1 (USBPCR1) has a USB_SEL flag that appears to 
> select different OTG implementations: Mentor or Synopsys!

The 3.18 patches do add functions to control this but I do not know if they are
used anywhere.

> 
> However, I see that the jz4780_otg_phy functions already access OPCR and 
> USBPCR, and I suppose that they do not need to change USBPCR1.

It seems as if USBPCR1 is for the EHCI/OHCI and USBPCR0 for the OTG port.

Have you had already a chance to run the code?

BR,
Nikolaus



More information about the Letux-kernel mailing list