[Letux-kernel] [PATCH] omap5: Fix reboot DPLL lock failure when using ABE TIMERs

[Tony Lindgren]

* Tony Lindgren <tony at atomide.com> [200817 06:42]:
> Hi,
> 
> * David Shah <dave at ds0.me> [200808 10:03]:
> > Having the ABE DPLL ref and bypass muxes set to different inputs was
> > causing the DPLL not to lock  when TIMER8 was used, as it is in the Pyra
> > for the backlight.
> > 
> > This patch fixes this by setting abe_dpll_bypass_clk_mux to sys_32k_ck
> > in omap5xxx_dt_clk_init.
> > 
> > A similar patch may also be needed for OMAP44xx which has similar code
> > in omap4xxx_dt_clk_init, but I have not added this as I have no hardware
> > to test on.
> > 
> > Signed-off-by: David Shah <dave at ds0.me>
> 
> Adding Tero to Cc.

David, care to resend this to the clock maintainers for applying?

To me it looks like the maintainers have not seen this one, try with:

$ scripts/get_maintainer.pl -f drivers/clk/ti/clk-54xx.c
Tero Kristo <t-kristo at ti.com> (maintainer:TI CLOCK DRIVER)
Michael Turquette <mturquette at baylibre.com> (maintainer:COMMON CLK FRAMEWORK)
Stephen Boyd <sboyd at kernel.org> (maintainer:COMMON CLK FRAMEWORK)
linux-omap at vger.kernel.org (open list:TI CLOCK DRIVER)
linux-clk at vger.kernel.org (open list:COMMON CLK FRAMEWORK)
linux-kernel at vger.kernel.org (open list)

Regards,

Tony

> > ---
> >  drivers/clk/ti/clk-54xx.c | 12 +++++++++++-
> >  1 file changed, 11 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c
> > index a4c5be533fbf..0a998e0e7d3b 100644
> > --- a/drivers/clk/ti/clk-54xx.c
> > +++ b/drivers/clk/ti/clk-54xx.c
> > @@ -617,7 +617,7 @@ static struct ti_dt_clk omap54xx_clks[] = {
> >  int __init omap5xxx_dt_clk_init(void)
> >  {
> >  	int rc;
> > -	struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
> > +	struct clk *abe_dpll_ref, *abe_dpll, *abe_dpll_byp, *sys_32k_ck, *usb_dpll;
> >  
> >  	ti_dt_clocks_register(omap54xx_clks);
> >  
> > @@ -628,6 +628,16 @@ int __init omap5xxx_dt_clk_init(void)
> >  	abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux");
> >  	sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
> >  	rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
> > +
> > +	/* 
> > +	 * This must also be set to sys_32k_ck to match or
> > +	 * the ABE DPLL will not lock on a warm reboot when
> > +	 * ABE timers are used.
> > +	*/
> > +	abe_dpll_byp = clk_get_sys(NULL, "abe_dpll_bypass_clk_mux");
> > +	if (!rc)
> > +		rc = clk_set_parent(abe_dpll_byp, sys_32k_ck);
> > +
> >  	abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
> >  	if (!rc)
> >  		rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ);
> > -- 
> > 2.27.0
> >