[Letux-kernel] [PATCH 00/20] A bunch of JZ4730 fixups for letux-kernel

[Paul Boddie]

On Wednesday, 30 December 2020 15:10:05 CET H. Nikolaus Schaller wrote:
> 
> Only, the hrtimer which is calculated from that 56 Hz should run at least at
> that speed to catch and count the wrap-arounds.

Right. I'll discuss the mechanism below.

> I have found another symptom of this issue besides sleep 10 needing 20
> seconds. The LEDs can be set to use the heartbeat trigger. And that blinks
> at half speed compared to all other systems I have.

[...]

> Which counter on the chip is used for that so that I could check its
> settings with devmem2?

Unless I am mistaken, the r4k_read_sched_clock function (arch/mips/kernel/
csrc-r4k.c) will be used, and this takes advantage of the Count coprocessor 
register (CP0 register 9 select 0).

Reading this is not a matter of just reading from memory, however. You need to 
have assembly language code to achieve the read operation, which is what 
read_c0_count does, it being defined in arch/mips/include/asm/mipsregs.h, 
expanding to...

__read_32bit_c0_register($9, 0)

...which expands to...

mfc0 <register>, $9

...maybe also including some kind of no-op or barrier instruction afterwards.

As for the mechanism by which this counter produces interrupts, there is 
another coprocessor register, Compare (CP0 register 11, select 0), which 
indicates the counter value at which an interrupt shall occur.

The setting of the Compare register with the next Count value to cause an 
interrupt is done in the mips_next_event function (arch/mips/kernel/cevt-
r4k.c). Initialisation of the interrupt and the "delta" between interrupts is 
done in the r4k_clockevent_init function.

I suppose that if the "delta" is too large, it will miss wraparounds occurring 
in the timer counter. So, perhaps we need to look at what the delta is.

[...]

> Sorry that I didn't review earlier :) That is the benefit of team-work.
> It gives higher quality (even if the first proposal, i.e. yours, is
> already very good). And combining review and real world testing is also
> beneficial.
> 
> What else is new: I have played with PWM. The chip is not enabled but
> has been programmed for a duty cycle 0. If I devmem2 a duty cycle and
> set the enable pin the backlight goes on and is controllable. This
> means that we have a proper setup of the pinctrl now.

Great!

> Unfortunately the LCD is not showing anything, despite an /dev/fb0 existing.
> So our LCD controller isn't doing what it should. Could also be a clock
> issue. But backlight only going off and not on is a sign of more subtle
> issues (like those from CI20 HDMI...).

We can certainly read the LCD controller registers and see if things are being 
set up properly.

> Anyways I have now consolidated all recent patches, merged everything
> and started to build 5.11-rc1 and 5.10.4 etc. So the trees and new patches
> will arrive in the next hours.
> 
> There is also an update for [1].
> 
> BR,
> Nikolaus
> 
> [1]: https://projects.goldelico.com/p/gta04-kernel/issues/951/#ic3302

I'll look forward to seeing the updated branch.

Thanks for investigating the different issues and troubleshooting the many 
problems! Sorry for the delay in responding.

Paul