[Letux-kernel] [PATCH 00/20] A bunch of JZ4730 fixups for letux-kernel

[Paul Boddie]

On Sunday, 27 December 2020 23:25:30 CET H. Nikolaus Schaller wrote:
> 
> So we have to spend a little more time in reverse engineering the behaviour
> of the SR flags and their relation to interrupts.
> 
> Hm. Is it possible to read the interrupt request register without triggering
> an interrupt? Then I can easily try to deduce from examples which bits are
> or-ed together to form the I2C-IRQ... Should be ICSR at 0x10001000, right?
> And there BIT(1). Even if interrupts are disabled by the kernel. I just
> have to enable IEN in the I2CCR.

Sorry to be slow in getting back to you!

Yes, it should be possible to examine ICSR (at 0x10001000), testing the I2C 
bit (bit 1), to see whether a condition applies to the peripheral.

Although some manuals for CPUs can be a bit vague about whether a condition 
will occur if interrupts are disabled, I seem to remember that the JZ-series 
will allow interrupt conditions to occur regardless of whether interrupt 
requests (IRQs) may occur.

It seems that the pending register (ICPR, at 0x10001010) would be used to test 
only for conditions that are not masked, with the mask registers effectively 
silencing conditions present in ICSR so that they would not appear in ICPR.

At the top level, of course, is the CPU's own interrupt register and handling, 
but we shouldn't have to worry too much about that.

Paul