[Letux-kernel] u-boot for e60k02
Andreas Kemnade
andreas at kemnade.info
Thu Oct 3 19:30:35 CEST 2019
On Thu, 3 Oct 2019 13:19:22 +0200
"H. Nikolaus Schaller" <hns at goldelico.com> wrote:
> > Am 03.10.2019 um 09:45 schrieb H. Nikolaus Schaller <hns at goldelico.com>:
> >
> > Forgot to share the repo link: http://git.goldelico.com/?p=letux-uboot.git;a=shortlog;h=refs/heads/e60k02
> >
> >> Am 03.10.2019 um 09:38 schrieb H. Nikolaus Schaller <hns at goldelico.com>:
> >>
> >> Hi,
> >> I have cleaned up a lot of compiler warnings so that it is easier
> >> to find real bugs...
> >>
> >> There remain a handful of undefined/undeclared functions which
> >> do not seem to harm the build process.
> >>
> >> What I have not checked is if the u-boot (compiled for kobo/clara
> >> as mx6sll_ntx_lpddr2_512m) still works as before.
>
> Seems to basically work (even if initialized for the wrong SoC).
>
> U-Boot 2016.03-g645fc0a (Oct 03 2019 - 11:44:14 +0200)
>
> CPU: Freescale i.MX6SL rev1.3 996 MHz (running at 792 MHz)
>
> ^^^ MX6SL identified
>
> CPU: Commercial temperature grade (0C to 95C) at 33C
> Reset cause: POR
> Board: MX6SLL LPDDR2 NTX
>
> ^^^ thinks it is the MX6SLL board
>
> I2C: ready
> DRAM: 512 MiB
> __get_sd_number(),cfg23=1,cfg24=0
> force_idle_bus: sda=0 scl=0 sda.gp=0x4d scl.gp=0x4c
> force_idle_bus: sda=0 scl=0 sda.gp=0x4f scl.gp=0x4e
> force_idle_bus: sda=0 scl=0 sda.gp=0x56 scl.gp=0x55
> force_idle_bus: failed to clear bus, sda=0 scl=1
> MMC: board_mmc_init() : isd=1
> board_mmc_init() : wifi=2
> FSL_SDHC: 0, FSL_SDHC: 1
> *** Warning - MMC init failed, using default environment
>
> ^^^ I have seen in code that there is something commented out
> ^^^ for SDHC/mmc initialization
>
> In: serial
> Out: serial
> Err: serial
> ntx_hw_early_init() 0
> ram p=80000000,size=536870912
> mmc read 0x9ffffe00 0x3ff 0x1
> binary magic @ sector no. 1024 not found !
> "hwcfg" not exist !!
> warning : ntxhwcfg not exist !
> ntx_hw_late_init()
> mmc read 0x9ffffe00 0x3ff 0x1
> binary magic @ sector no. 1024 not found !
> "hwcfg" not exist !!
> mmc read 0x9ffffe00 0x1 0x1
> NTXSN not avalible !
> _led_R(0) : cannot work without ntx hwconfig !
> ntx_gpio_get_value(404) : error parameter ! null ptr !
> ** Block device MMC 0 not supported
> check_and_clean: reg 0, flag_set 0
> Fastboot: Normal
> Net: CPU Net Initialization Failed
> No ethernet found.
> Hit any key to stop autoboot: 0
> mmc read 0x80800000 0x7ff 0x1
> no kernel image signature !
> mmc read 0x80800000 0x800 0x2400
> Booting from mmc ...
> mmc read 0x83000000 0x505 0x1
> no dtb signature !
> WARN: Cannot load the DT
> eBR-1A #
> eBR-1A # mmc info
> eBR-1A #
>
> >>
> >> And I have not tried the tolino/shine3 (mx6sl_ntx_lpddr2_512m) binary
> >> either...
>
> Ok, I was courageous and tried the version with what we believe is the correct MX6SL pinmux.
> No yellow smoke. The only hot (warm) spot by looking through the thermal camera is the SoC (27°C).
>
> Boot log:
>
> U-Boot 2016.03-g645fc0a (Oct 03 2019 - 12:37:57 +0200)
>
> CPU: Freescale i.MX6SL rev1.3 996 MHz (running at 792 MHz)
> CPU: Commercial temperature grade (0C to 95C) at 33C
> Reset cause: POR
> Board: MX6SLL LPDDR2 NTX
>
> ^^^ seems to be a constant string and not depend on real SoC
>
> I2C: ready
> DRAM: 512 MiB
> __get_sd_number(),cfg23=1,cfg24=0
> force_idle_bus: sda=0 scl=0 sda.gp=0x4d scl.gp=0x4c
> force_idle_bus: sda=0 scl=0 sda.gp=0x4f scl.gp=0x4e
> force_idle_bus: sda=1 scl=0 sda.gp=0x56 scl.gp=0x55
> MMC: board_mmc_init() : isd=1
> board_mmc_init() : wifi=2
> FSL_SDHC: 0, FSL_SDHC: 1
> *** Warning - bad CRC, using default environment
>
> ^^^ same failure as before
>
if there is no environment there (in tolino firstpart)
that is no bug. I have a script to add an env there.
> In: serial
> Out: serial
> Err: serial
> ntx_hw_early_init() 0
> ram p=80000000,size=536870912
> switch to partitions #0, OK
> mmc0 is current device
> mmc read 0x9ffffe00 0x3ff 0x1
>
> MMC read: dev # 0, block # 1023, count 1 ... 1 blocks read: OK
> mmc read 0x9ffffe00 0x400 0x1
>
> ^^^ looks better!
>
> MMC read: dev # 0, block # 1024, count 1 ... 1 blocks read: OK
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=0
>
> ^^^ this is new
>
interesting thing is whether it was tried before or not tried because
of mmc problems.
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=1
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=2
> i2c_init_transfer: give up i2c_regs=0x21a8000
> RC5T619 write to [0x11] 1 bytes failed !!
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=0
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=1
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=2
> i2c_init_transfer: give up i2c_regs=0x21a8000
> RC5T619 read [0xb] failed !!
> RC5T619_enable_watchdog():read reg0xb error -1ntx_hw_late_init()
>
> ^^^ the i2c issue seems to be the i2c where the RC5T619 is connected to.
>
can you try out via cmdline whether other i2c devices are accessible,
esp. backlight on i2c1?
Found something interesting in the i2c pinmux.
IOMUX_CONFIG_SION = 0x10
For some reason we do not have that is the kernel (and not in the
kernel-imported pinmuxes used for i2c2 and i2c3):
./arch/arm/include/asm/arch-mx6/mx6sll_pins.h: MX6_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x0464, 0x019C, IOMUX_CONFIG_SION | 0, 0x067C, 0, 0),
./arch/arm/include/asm/arch-mx6/mx6sll_pins.h: MX6_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0468, 0x01A0, IOMUX_CONFIG_SION | 0, 0x0680, 0, 0),
./arch/arm/include/asm/arch-mx6/mx6sl_pins.h: MX6_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0450, 0x0160, 0x10, 0x0720, 2, 0),
./arch/arm/include/asm/arch-mx6/mx6sl_pins.h: MX6_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x044C, 0x015C, 0x10, 0x071C, 2, 0),
./arch/arm/include/asm/arch-mx6/mx6sl-pins-kernel.h:MX6SL_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x44c,0x15c,0x0,0x71c,0x2,0),
./arch/arm/include/asm/arch-mx6/mx6sl-pins-kernel.h:MX6SL_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x450,0x160,0x0,0x720,0x2,0),
so maybe we just need to add that 0x10 to the I2C2 and I2C3 pinmuxes.
> mmc read 0x9ffffc00 0x1 0x1
>
> MMC read: dev # 0, block # 1, count 1 ... 1 blocks read: OK
> NTXSN not avalible !
> ntx_gpio_get_value(404) : error parameter ! null ptr !
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=0
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=1
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=2
> i2c_init_transfer: give up i2c_regs=0x21a8000
> RC5T619 read [0xbd] failed !!
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=0
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=1
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=2
> i2c_init_transfer: give up i2c_regs=0x21a8000
> RC5T619 write to [0xb6] 1 bytes failed !!
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=0
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=1
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=2
> i2c_init_transfer: give up i2c_regs=0x21a8000
> RC5T619 write to [0xb8] 1 bytes failed !!
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=0
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=1
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=2
> i2c_init_transfer: give up i2c_regs=0x21a8000
> RC5T619 write to [0xb7] 1 bytes failed !!
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=0
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=1
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=2
> i2c_init_transfer: give up i2c_regs=0x21a8000
> RC5T619 write to [0xb7] 1 bytes failed !!
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=0
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=1
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=2
> i2c_init_transfer: give up i2c_regs=0x21a8000
> RC5T619 read [0xb7] failed !!
> REGISET2 val 9E
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=0
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=1
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=2
> i2c_init_transfer: give up i2c_regs=0x21a8000
> RC5T619 write to [0xb7] 1 bytes failed !!
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=0
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=1
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=2
> i2c_init_transfer: give up i2c_regs=0x21a8000
> RC5T619 read [0xb7] failed !!
> REGISET2 val 9E
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=0
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=1
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=2
> i2c_init_transfer: give up i2c_regs=0x21a8000
> RC5T619 write to [0xb7] 1 bytes failed !!
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=0
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=1
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=2
> i2c_init_transfer: give up i2c_regs=0x21a8000
> RC5T619 read [0xb7] failed !!
> REGISET2 val 9E
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=0
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=1
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=2
> i2c_init_transfer: give up i2c_regs=0x21a8000
> RC5T619 write to [0xb7] 1 bytes failed !!
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=0
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=1
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=2
> i2c_init_transfer: give up i2c_regs=0x21a8000
> RC5T619 read [0xb7] failed !!
> REGISET2 val 9E
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=0
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=1
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=2
> i2c_init_transfer: give up i2c_regs=0x21a8000
> RC5T619 write to [0xb7] 1 bytes failed !!
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=0
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=1
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=2
> i2c_init_transfer: give up i2c_regs=0x21a8000
> RC5T619 read [0xb7] failed !!
> REGISET2 val 9E
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=0
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=1
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=2
> i2c_init_transfer: give up i2c_regs=0x21a8000
> RC5T619 write to [0xb7] 1 bytes failed !!
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=0
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=1
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=2
> i2c_init_transfer: give up i2c_regs=0x21a8000
> RC5T619 read [0xb7] failed !!
> REGISET2 val 9E
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=0
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=1
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=2
> i2c_init_transfer: give up i2c_regs=0x21a8000
> RC5T619 write to [0xb7] 1 bytes failed !!
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=0
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=1
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=2
> i2c_init_transfer: give up i2c_regs=0x21a8000
> RC5T619 read [0xb7] failed !!
> REGISET2 val 9E
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=0
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=1
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=2
> i2c_init_transfer: give up i2c_regs=0x21a8000
> RC5T619 write to [0xb7] 1 bytes failed !!
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=0
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=1
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=2
> i2c_init_transfer: give up i2c_regs=0x21a8000
> RC5T619 read [0xb7] failed !!
> REGISET2 val 9E
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=0
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=1
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=2
> i2c_init_transfer: give up i2c_regs=0x21a8000
> RC5T619 write to [0xb7] 1 bytes failed !!
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=0
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=1
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=2
> i2c_init_transfer: give up i2c_regs=0x21a8000
> RC5T619 read [0xb7] failed !!
> REGISET2 val 9E
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=0
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=1
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=2
> i2c_init_transfer: give up i2c_regs=0x21a8000
> RC5T619 write to [0xb7] 1 bytes failed !!
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=0
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=1
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=2
> i2c_init_transfer: give up i2c_regs=0x21a8000
> RC5T619 read [0xb7] failed !!
> REGISET2 val 9E
> ntx_config_fastboot_layout():8 binaries partition added
> ntx_config_fastboot_layout: get partition:media fail !!
> ntx_config_fastboot_layout: get partition:system fail !!
> ntx_config_fastboot_layout: get partition:data fail !!
> ntx_config_fastboot_layout: get partition:cache fail !!
> ntx_config_fastboot_layout: get partition:recovery fail !!
> ntx_config_fastboot_layout: get partition:vendor fail !!
> ntx_config_fastboot_layout: get partition:misc fail !!
> ntx_config_fastboot_layout: get partition:emergency fail !!
> ntx_config_fastboot_layout():9 mbr partition added
>
> ^^^ is this the same on Kobo?
>
so I guess you have the tolino firstpart things and not the kobo ones.
Never seen this on kobo. I guess especially the hwcfg makes us enter
rarely used codepaths it the patched kobo uboot.
> check_and_clean: reg 0, flag_set 0
> Fastboot: Normal
> Net: CPU Net Initialization Failed
> No ethernet found.
> Hit any key to stop autoboot: 0
> switch to partitions #0, OK
> mmc0 is current device
> mmc read 0x80800000 0x7ff 0x1
>
> MMC read: dev # 0, block # 2047, count 1 ... 1 blocks read: OK
>
> ^^^ cool!
>
> kernel size = 2920156 at 80800000
> mmc read 0x80800000 0x800 0x164d
>
> MMC read: dev # 0, block # 2048, count 5709 ... 5709 blocks read: OK
> Booting from mmc ...
> mmc read 0x83000000 0x505 0x1
>
> MMC read: dev # 0, block # 1285, count 1 ... 1 blocks read: OK
> no dtb signature !
>
> ^^^ ok, I have not saved any DTB at the locations where the ntx loader is looking at.
>
> WARN: Cannot load the DT
> eBR-1A # mmc info
> Device: FSL_SDHC
> Manufacturer ID: 74
> OEM: 4a60
> Name: USD
> Tran Speed: 50000000
> Rd Block Len: 512
> SD version 3.0
> High Capacity: Yes
> Capacity: 7.5 GiB
> Bus Width: 4-bit
> Erase Group Size: 512 Bytes
> eBR-1A # mmc part
>
> Partition Map for MMC device 0 -- Partition Type: DOS
>
> Part Start Sector Num Sectors UUID Type
> 1 49152 15710208 affc6b85-01 83
> eBR-1A #
> eBR-1A # ext4load mmc 0:1 ${loadaddr} boot/uImage
> 5073192 bytes read in 319 ms (15.2 MiB/s)eBR-1A # bootm ${loadaddr}
> ## Booting kernel from Legacy Image at 80800000 ...
> Image Name: Linux-4.19.73-letux+
>
> ^^^ first Letux kernel load successful
>
> Created: 2019-09-16 9:36:09 UTC
> Image Type: ARM Linux Kernel Image (uncompressed)
> Data Size: 5073128 Bytes = 4.8 MiB
> Load Address: 80008000
> Entry Point: 80008000
> Verifying Checksum ... OK
> Loading Kernel Image ... OK
> bootargs console=ttymxc0,115200 rootwait rw no_console_suspend
>
> hwcfgp=9ffffe00,pcb=74,customer=0
>
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=0
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=1
> wait_for_sr_state: failed sr=81 cr=a0 state=2020
> i2c_init_transfer: failed for chip 0x32 retry=2
> i2c_init_transfer: give up i2c_regs=0x21a8000
> RC5T619 read [0xbd] failed !!
> ntx_gpio_get_value(404) : error parameter ! null ptr !
> ESDin=0,UPGKey=-1,PWRKey=0,USBin=0x0,BootESD=0,MenuKey=0
> mmc read 0x9ffffc00 0x37ff 0x1
>
> MMC read: dev # 0, block # 14335, count 1 ... 1 blocks read: OK
> mmc read 0x9fae1400 0x3800 0x28f5
>
> MMC read: dev # 0, block # 14336, count 10485 ... 10485 blocks read: OK
> mmc read 0x9fae1200 0x405 0x1
>
> MMC read: dev # 0, block # 1029, count 1 ... 1 blocks read: OK
> [WARNING] Binaries load sequence should Lo->Hi !
> mmc read 0x9fadee00 0x406 0x13
>
> MMC read: dev # 0, block # 1030, count 19 ... 19 blocks read: OK
> Kernel RAM visiable size=506M->506M
> hwcfg rootfstype : 2
> hwcfg partition type : 11
> No gpc device node -9, force to ldo-enable.
>
> Starting kernel ...
>
> ... then it hangs. Which is to be expected if there is no DTB.
>
> Anyways we have made a big step forwards.
>
> So the next steps are IMHO:
retry with kobo firstpart (with m6sl uboot) to check whether things
work.
> 1. fix the i2c issue on the Tolino - and potential other NTXGPIO setup issues
which might be fixed by that.
> 2. get rid of the ntx special loader code that wants to see the 9 fastboot partitions
is probably also fixed by that (switch from android mode to ordinary
linux by different hwcfg).
Well, I think it is a good idea to be still able to boot the
kobo kernel (or even convert the pinmuxes there to mx6sl). Or be able
to copy code from there for first steps towards epdc, e.g. So
I would not restructurize it too much in a first step.
If we have a good kernel, then the time is there to do it.
> 3. make u-boot simply load uImage from /boot/uImage
well, maybe my bootchoice thing now works (which is included in the
kobo-firstpart), would be interesting
to verify. Then a /boot/boot.scr is loaded.
> 4. make it load the device tree and set the address
load_ntxkernel
run loadfdt
setenv bootargs console=ttymxc0,115200 rootwait rw root=/dev/mmcblk0p5
setenv fdtfile imx6sl-tolino-shine3.dtb
load mmc 0:5 ${loadaddr} /boot/zImage
load mmc 0:5 ${fdt_addr} /boot/dtb/${fdtfile}
bootz ${loadaddr} - ${fdt_addr}
Big attention: There is the quiet flag appended to cmdline in bootz.
For my experiments I have first renamed it in the kernel in init/main.c:
early_param("quiet", quiet_kernel);
But when you are already compiling uboot, you might remove the flag
there, of course.
I think before we tidy up uboot too much, maybe we should have a first
look on the kernel, just to see if our assumptions about the hardware
are correct without having mysterious, hacky uboot things influence our
sight. The kobo/backlight branch on github.com/akemnade/linux.git might
be the best thing now to try (not the mysterious 5.4-rc1).
It includes a tolino dtb. Maybe enabling some CONFIG_REGULATOR_DEBUG
might be interesting.
Anything influencing the boot process should imho go into a separate
branch, so we can maybe be prepared for dualboot things. The
kobolino uboot probably boots the android system also.
Regards,
Andreas
PS: 2/3 of my backlight patches are now accepted. So we have some
progress there.
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