[Letux-kernel] 2GB vs. 4GB Pyra RAM tests

[Dr. H. Nikolaus Schaller]

Hi, Great! Thanks!
We may have doubled the noise on ddr3  power with 4gb chips. New pcb layout may already be better.
Will try to test asap.

On the road.

> Am 14.08.2017 um 06:39 schrieb Tony Lindgren <tony at atomide.com>:
> 
> Hi,
> 
> * H. Nikolaus Schaller <hns at goldelico.com> [170811 13:25]:
>>> Am 11.08.2017 um 16:46 schrieb Tony Lindgren <tony at atomide.com>:
>>> and I noticed
>>> it would hang often while booting even with 2GB and no LPAE.
>>> I only saw any kind of oops once or twice, most of the time
>>> it just hung. Is this what you're seeing too?
>> 
>> Yes. 4GB CPU board randomly hangs - or succeeds to boot. 2GB boards
>> seem to boot fine every time.
> 
> So after tinkering with pyra-4g this weekend, here's what
> seems to work based on very light testing:
> 
> 1. Configure smps6 to 1.39V instead of 1.35V
> 
> So what does this mean? Not enough power from palmas or too
> low voltage for the 4GB DDR3 chip? Any ideas?
> 
> The 4GB DDR3 datasheet says "1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)",
> so maybe we need to configure it to 1.35V separately somehow?
> 
> 2. Configure interleaving
> 
> Not sure if this is mandatory but needed for now it seems.
> 
> 3. Use igepv5 ddr3 timings instead of Matthij's timings
> 
> Have not checked what's different.. I'll post my WIP patches
> shortly and let's figure it out, maybe Matthijs can spot
> the differences :)
> 
>> That is the reason why we don't know for sure if it is a SW or HW effect.
>> It could also be HW induced because SW setup is not optimized.
> 
> Well the 1.39V need seems weird..
> 
>> AFAIK, there is a DRA7 tool to calculate some EMIF parameter block
>> which takes wire lengths from SoC to DDR3 into account. The EMIF
>> seems to be able to add some picoseconds here and there...
> 
> No idea about that, sounds like somebody who is more familiar
> with memory timings should try it out.
> 
>> We haven't done (and probably can't do) that for OMAP5 and Pyra.
>> And I don't exactly know where Mattijs got our EMIF setup from (maybe
>> IGEP5 wich different DDR3 PCB layout):
>> 
>> http://git.goldelico.com/?p=gta04-uboot.git;a=blobdiff;f=board/goldelico/letux-cortex15/lc15.c;h=280da2095da9a780475fe3d59e79d283b050f02d;hp=709865cbe0f10d389634924d3b57c5731c184429;hb=0c5e26e7886ea7d2d934f65e2e6cbf15a2b52bc8;hpb=be096ca0c2b204897b84c45e709511184b3a4059
> 
> Well something is still different with timings as the igepv5
> timings work now :p
> 
> $ cat /proc/cmdline
> console=ttyS2,115200 mem=2032M at 0x80000000 mem=2048M at 0x300000000 debug earlyprintk earlycon
> $ free
>             total       used       free     shared    buffers     cached
> Mem:       4115788     186528    3929260     149784          0     149784
> -/+ buffers/cache:      36744    4079044
> Swap:            0          0          0
> 
>> PS: if you can use a JTAG adapter, I could send you a SD-Card shaped
>> PCB with solder points for the OMAP5 JTAG signals. Here is a photo
>> (of the uncut PCB - I haven't access to a better photo this week):
> 
> I have not really needed JTAG for years, maybe a bit later thanks :)
> 
> Regards,
> 
> Tony