[Letux-kernel] 1.5GHz problems
H. Nikolaus Schaller
hns at goldelico.com
Sat Jul 30 20:02:14 CEST 2016
> Am 30.07.2016 um 19:53 schrieb H. Nikolaus Schaller <hns at goldelico.com>:
>> Am 29.07.2016 um 19:45 schrieb Grazvydas Ignotas <notasas at gmail.com>:
>> On Fri, Jul 29, 2016 at 5:00 PM, H. Nikolaus Schaller <hns at goldelico.com> wrote:
>>> G) [Kernel] omap5 mpu bridge dividers
>>> Matthijs recently reported a potential issue here with the above subject
>>> A simple test would be to boot at 1.5Ghz and then run
>>> omapconf write 0x4A004320 0x06000001
>>> But I can't even boot at 1.5Ghz so I have no chance to test.
>> It used to be possible to select default cpufreq governor in .config
>> or maybe kernel arguments, so perhaps you could try booting with
>> powersave governor, change the divider and then switch to the
>> performance governor.
> good idea!
> Was a little more difficult. I had to
> 1. change defconfig
> # CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
> -# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
> # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
> +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
> 2. echo "ENABLE=false" >$SD/etc/default/cpufrequtils
> or Debian would try to enable the ondemand govenor at the end of the
> boot process.
> 3. After adding two OPP for 1.25GHz and 1.5GHz to DT I could run
> additional tests.
> cpufreq-set -f 1Ghz runs fine. No problems.
> cpufreq-set -f 1.25GHz might hang
> cpufreq-set -f 1.5GHz hangs almost immediately within a second or so. Even as the CPU is almost idle (waiting for shell and blinking LEDs)
> 4. Clock divider
> devmem2 0x4A004320 w 0x06000001
> /dev/mem opened.
> Memory mapped at address 0xb6fae000.
> Value at address 0x4A004320 (0xb6fae320): 0x1000001
> Written 0x6000001; readback 0x6000001
> has no obvious influence. Neither @500 MHz nor @1.5GHz.
> So unfortunately we do not know more than before.
> The only thing that remains really stable is that the board is instable @>1GHz.
> We simply do not know the handle to turn for an improvement.
> And we all can imagine a lot of handles... The trick is to find the
> right one.
Ah, there is room for another test for the hardware now!
The CPU board I am running these test on has additional wires which allow
to measure the voltages VDD_MPU, VDD_CORE, VDD_DDR3, VDD_MM,
So I can better look what happens as soon as the cpufreq-set -f 1.5GHz
command is started. For example if the voltages become more noisy or
something significant changes. E.g. if they are really what the DT OPP
Will do as soon as I find time to make this setup.
Anyways, please all kernel developers think about potential kernel
issues (scheduling, SMP, locking, interrupts, I&D-caches) that might
lead to such a behaviour. And potential tests (I can add printk etc.
One thing I also want to mention: the DDR3 speed remains the same
(I think 532 MHz) in all these experiments. So an A15 running at 1.5GHz
might have to wait longer for external RAM than I&D-cache which gives
different execution patterns.
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